Requirements

• BSc/MSc in Electrical Engineering or Computer Science
• 5+ years of experience in VLSI industry
• Strong understanding of: RTL design, Synthesis and netlist transformations, low-power design ( UPF concepts)
• Hands-on experience with LEQ tools ( Cadence Conformal , Synopsys Formality )
• Strong debugging and scripting skills ( TCL, Python )

Nice to Haves

• Experience with power-aware LEQ and low-power verification flows
• Familiarity with synthesis and PnR flows
• Experience in large-scale SoC environments and multi-site collaboration
• Exposure to ECO flows and late-stage sign-off methodologies
• Experience working with EDA vendors and driving tool improvements

What You'll Be Doing

• Develop, deploy, and support equivalence checking methodologies across complex SoC programs
• Ensure functional correctness between RTL, synthesized netlists, and post-implementation designs
• Drive scalable, robust sign-off flows