Senior Mask Layout Design Engineer

Requirements

• BS in Electrical Engineering (or equivalent experience)
• At least 5+ years of hands-on layout design experience
• Deep understanding of analog circuit layout concepts in submicron CMOS technologies
• Validated experience with Cadence custom circuit design tools
• Experience running and debugging DRC and LVS with verification tools
• Ability to work optimally in a team, good interpersonal skills and positive energy
• Proficiency in scripting languages like perl, python, skill etc

What You'll Be Doing

• The role entails working collaboratively and multi-functionally with a multi-disciplinary team
• Performing physical layout for mixed-signal functions in state-of-the-art sub-micron CMOS technologies
• Customizing designs for integration in VLSI products
• Conducting floor planning, custom layout and verifying against design rules and schematics
• Handling fill, post-processing, DRC mitigation, and foundry interactions