Requirements

Proven experience in developing structured RTL designs with System Verilog or VHDL.
Possesses outstanding RTL/Netlist debugging skills to effectively resolve technical challenges in simulation and silicon development.
Expertise in designing complex systems with Clock/Reset Domain Crossings and power domains.
Proficient in day-to-day usage of scripting languages (TCL, Python, Perl, shell), Linux, and revision control systems, database management, and releases.
Proven track record to meet ambitious deadlines and maintain productivity.
Excellent problem-solving skills and the capacity to find effective technical solutions between partners in RTL-design, firmware, system engineering, power, and physical design teams.
English language proficiency is required.

Preferred Qualifications

Experience with synthesis, logic equivalence, or ECO techniques would be highly beneficial.
The ideal candidate demonstrates a strong passion for owning/driving design schedules using well-defined metrics, exhibiting initiative, and taking ownership of responsibilities.
Experience with AXI/AHB bus fabric and processor sub-systems would be a huge asset.
A bachelor's or master’s in Electrical Engineering, Communication Engineering, Computer Science/ Software Engineering, or equivalent.

Responsible for crafting sophisticated digital IPs that control all major system components.
Collaborate closely with system architects, firmware teams, verification engineers, and other stakeholders to develop block-level specifications and implement the designs.
Own the creation of the blocks and guide them through the concept, design, integration, and verification phases.

Smart people and inspiring, innovative technologies are the norms at Apple.
Opportunity to develop and integrate Control IPs for the next generations of Cellular Transceiver SoCs.
Commitment to inclusion and diversity with equal opportunity for all applicants.
Reasonable accommodation provided to applicants with physical and mental disabilities.