CAD Logic Equivalence Checking (LEQ) Engineer - m/f/d

Requirements

• BSc/MSc in Electrical Engineering or Computer Science
• 5+ years of experience in VLSI industry
• Strong understanding of: RTL design, Synthesis and netlist transformations, low-power design (UPF concepts)
• Hands-on experience with LEQ tools (Cadence Conformal, Synopsys Formality)
• Strong debugging and scripting skills (TCL, Python)

Nice to Haves

• Experience with power-aware LEQ and low-power verification flows
• Familiarity with synthesis and PnR flows
• Experience in large-scale SoC environments and multi-site collaboration
• Exposure to ECO flows and late-stage sign-off methodologies
• Experience working with EDA vendors and driving tool improvements

What You'll Be Doing

• Developing, deploying, and supporting equivalence checking methodologies across complex SoC programs
• Ensuring functional correctness between RTL, synthesized netlists, and post-implementation designs
• Driving scalable, robust sign-off flows

Perks and Benefits

• Outstanding career opportunities for interns interested in developing Apple’s groundbreaking methodologies
• Opportunity to work with industry's best and innovate the design of computer chips
• Chance to provide the next technological leap and improve customer experiences