RF Design Engineer (m/f/d)

Requirements

• Profound experience in RF circuit design techniques.
• Experience with Cadence design tools.
• EM modelling and simulation skills.
• MSEE /PhD or equivalent is required.
• Proficiency in English is required.

Nice to Haves

• A proven track record in RF, and analog integrated circuit design, with experience in wireless PLL circuit architectures in CMOS technologies.
• Deep understanding in PLL system specifications and the ability to work with system architects to translate system requirements into circuit requirements at IC block level.
• Knowledge in fundamental RF theories and concepts, such as innovative PLL concepts and their trade-offs in key performance parameters (KPI’s), area and power efficiency.
• The ability to optimize the overall PLL system including EVM, blocker requirements and crosstalk mitigations.
• Deep technical knowledge in analysis, design, and implementation of RF wireless low-noise, broadband and power efficient PLLs, as well as frequency converting blocks.
• Extensive experience in simulation of RF analog key building blocks, such as oscillators, frequency dividers, phase detectors and local oscillator signal distribution chains
• Solid experience in optimization of RF circuit design impairments by means of highly sophisticated methods of trimming and calibration
• Experience in RF cross talk analysis, understanding the critical RF cross talk building laws and the according aggressor and victim analysis, translation of RF system KPI's into IC block level isolation requirements
• Understanding of RF device modelling, insights into packaging effects, integrated coils, supply isolations, high frequency ESD structures, and circuit layout for optimum performance.
• Hands-on experience in high frequency silicon characterization and debugging on chip as well as on system level.

What You'll Be Doing

• Use your vast background in circuit design to provide PLL design solutions for wireless chips.
• Collaborate with platform architects, system group, and digital design group to define the requirements for a PLL lineup based on the product requirements.
• Work with the Apple technology team and silicon foundries on process evaluation/selection for the target device.
• Design various analog biasing blocks, oscillators, frequency dividers, and local oscillator chains.
• Integrate the IP’s and verify the top-level functionality and performance with system engineering, layout, and chip integration teams.
• Work with RF test engineers to bring up, characterize, and optimize new silicon.

Perks and Benefits

• The minimum salary pursuant to the applicable collective bargaining agreement amounts to €62,610 gross per year for full-time employment. Actual salaries are oriented at current market salaries and take your qualifications and experience into account.