CAD Tools Optimisation Engineer (Design Verification)

Requirements

• Expert knowledge on Cadence tool chain
• Familiarity with SystemVerilog / Verilog / VHDL
• A curiosity about GPU / PMU / CPU / SOC architecture and micro-architecture

What You'll Be Doing

• Assisting with delivering high quality infrastructure for automating chip design processes
• Developing and deploying new methodologies with vendor and internal teams
• Supporting and debugging issues on large scale simulations

Perks and Benefits

• N/A