Requirements

• Knowledge of System Verilog test-bench language and UVM (Universal Verification Methodology)
• Hands-on experience with constrained random verification environments
• Basic design background in support of verification results analysis
• Knowledge of Object Oriented Programming (OOP)
• Proficiency in English language is required

Nice to Haves

• Master's degree or PhD in Electrical/Computer Engineering or proven industrial experience/degree equivalent
• Experience in AI/ML is desired
• Hands-on experience with Assertion-Based Verification
• Familiarity with system design using C++, Python or Verilog
• Familiarity with FPGA emulation platforms

What You'll Be Doing

• Definition and design of Self-checking verification environments for multi-layer systems using the SystemVerilog UVM library
• Performance-based analysis
• Power-related analysis and scenario design for early power estimation
• Deliveries of tests for design and test engineering teams
• Gate-level verification (power and timing)
• Lab bring-up support
• Focus on research and innovations to improve verification techniques and tools for mixed-signal systems in order to increase efficiency and quality

Perks and Benefits

• Apple is an Equal Opportunity Employer that is committed to inclusion and diversity
• Affirmative action to offer employment and advancement opportunities to all applicants, including minorities, women, protected veterans, and individuals with disabilities
• Apple will not discriminate or retaliate against applicants who inquire about, disclose, or discuss their compensation or that of other applicants