Requirements

• Knowledge of SystemVerilog and UVM
• Experience with SystemC, C/C++, Python/perl
• Ability to develop and establish DV Methodologies
• Ability to use LLMs and MCPs
• Ability to develop Python-based automation solutions
• Understanding of constraint random testing, SVA, Coverage driven verification
• Test planning and problem-solving skills

Nice to Haves

• BSc, MSc, or higher degree in Electrical Engineering/Computer Science, Embedded Engineering or similar
• Experience in C/C++ modeling for design verification
• Knowledge of 4G/5G cellular physical layer operation (3GPP)
• Experience with verification of embedded processor cores
• Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment
• Knowledge of using LLMs to improve efficiency and quality of verification
• Understanding of prompt engineering and LLM workflow optimization

What You'll Be Doing

• Lead verification efforts for next-generation cellular systems including baseband modems and RF link controllers
• Develop highly reusable UVM verification environments and comprehensive coverage-driven test cases
• Collaborate with multi-functional teams to validate complex IP and subsystem designs
• Drive methodology innovation by deploying sophisticated tools and techniques
• Work closely with product development teams to ensure tape-out readiness and enhance customer experiences globally
• Gain expertise in cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and debug methodologies
• Implement best-in-class design verification practices including co-verification with models and firmware