Requirements

• Strong knowledge of SystemVerilog and UVM
• Experience developing scalable and portable test-benches
• Experience with constrained random verification environments
• MS/BS in Computer Science or Electrical Engineering or equivalent
• Fluency in English language is required

Nice to Haves

• Experience defining coverage space, writing coverage model, analyzing results
• Experience with Assertion Based Verification
• Knowledge of Object Oriented Programming
• Experience in Formal Verification (Formal Linting, Formal connectivity, user property verification)
• Experience with Python, Perl or TCL
• Excellent communication and interpersonal skills combined with the ability to collaborate
• Basic knowledge of mixed signal verification

What You'll Be Doing

• Develop verification plans in coordination with design leads and architects
• Build and maintain verification test bench components and environments
• Generate directed and constrained random tests
• Run simulations and debug design and environment issues
• Build functional coverage points, analyze coverage, and improve test environment to target coverage holes
• Craft automated verification flows for block and chip level verification
• Apply knowledge of hardware description languages and verification languages to verify complex designs
• Work with block and core level engineers to ensure flawless verification flow