Requirements

• Knowledge of System Verilog and UVM.
• Experience with System C, C/C++, Python/perl.
• Ability to develop and establish DV Methodologies.
• Ability to use LLMs and MCPs.
• Ability to develop Python-based automation solutions.
• Understanding of constraint random testing, SVA, Coverage driven verification.
• Test planning and problem-solving skills.

Nice to Haves

• BSc, MSc. or higher degree in Electrical Engineering/Computer Science, Embedded Engineering or similar
• Experience in C/C++ modeling for design verification.
• Knowledge of 4G/5G cellular physical layer operation (3GPP).
• Experience with verification of embedded processor cores.
• Hands-on verification experience of Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment.
• Knowledge of using LLMs to improve efficiency and quality of verification.
• Understanding of prompt engineering and LLM workflow optimization.

What You'll Be Doing

• Designing and verifying innovative baseband modems and RF link controllers for Apple's SOCs.
• Developing comprehensive coverage-driven and directed test cases to validate complex IP and subsystem designs.
• Collaborating with multi-functional teams to drive methodology innovation and ensure tape-out readiness.
• Deploying sophisticated tools and techniques to elevate verification practices.
• Contributing to the delivery of cellular systems that redefine industry capabilities.

Perks and Benefits

This position offers exceptional opportunities to deepen your expertise across cellular protocols, complex IP and subsystem architectures, advanced fabric protocols, and sophisticated debug methodologies. You'll gain experience with best-in-class design verification practices, co-verification techniques with models and firmware, and industry-standard low-power architectures. Additionally, you'll have the chance to contribute to products that impact customers worldwide while advancing your technical expertise.